Category Archives: FPGA

J1a system on a Lattice ICESTICK40

Long time readers of this blog might remember that I received a Gameduino board designed by James Bowman. I used it to construct ANGST, an Arduino and Gameduino satellite tracking project. James did all the heavy lifting: the Gameduino uses a Xilinx FPGA to implement an Arduino shield that can generate graphics and sounds. To do so, it actually implements a “soft processor”, a very simple CPU core designed to execute the Forth Programming Language. I enjoyed goofing around with it, but it’s been sitting in a box for quite a while.

A couple months ago, I remember hearing about an interesting project called Project IceStorm. One of the things that has kept me from tinkering with FPGAs is that the development environments are proprietary and big. Really big. Wrapping my head around them just didn’t seem like fun. But Project Icestorm tries to apply open source methodology to FPGA programming. They reverse engineered the bitstream used by a simple family of FPGAs made by Lattice Semiconductor. The result is a complete set of tools to code logic designs in Verilog, compile, place, route and download them to a Lattice FPGA board. What’s doubly cool is that James took the core of his J1a processor and adapted it for a very cheap Lattice IceStick development board. Compared to some other FPGA boards, the Lattice ICE40 chips are pretty limited, but the J1a is a pretty good fit, and now with Project IceStorm, you can compile and download directly to the board, and have a small Forth base system running without any extra hardware.

I went ahead an ordered one of the boards, and following the instructions on James’ website, I went ahead and built the code and successfully installed in on my $21 ICESTICK. Initially, I had some trouble running the LED blink test: three of the leds worked fine, but two wouldn’t seem to light. Eventually, I tried updating the “yosys” software and recompiling it, and after that, it worked as expected. I’ve never done any Verilog programming before, but having this setup seems to make it seem more tractable than it has before. I’m dusting off the largely unused Verilog books I have on my shelf, and am thinking of trying something simple like a digital clock as my first try. I suspect I’ll outgrow the ICESTICK pretty quickly, but until I do, I bet I am going to learn a lot.

James does a better job describing his system than I could, so here’s a link to his video and his page describing the system. Thanks to Ken Boak for also drawing my attention to this project.

James’ page on J1a SwapForth

Papilio – An Introductory FPGA Kit

My own explorations of FPGA have been, well, slow. Well, let’s be truthful: since buying a BASYS-2 board, I have done little more than ensure that it powers up. But I’m still interested in FPGAs, and so I thought I’d draw attention to a board that I saw for the first time at the Maker Faire: the Papilio. For $50, you can get a cute little board with a 250K gate Xilinx FPGA on board (similar to the Gameduino, but it is an empty slate, upon which any design can be imposed, and it is meant to stand alone, not be chained to an Arduino). Expansion is provided via a series of “wings”: little plugin boards (smaller than the traditional Arduino shields) that include things like a joystick interface and a VGA interface. For around $100, you can get Papilio and a set of wings that can enable you to recreate some of the classic arcade games like PacMan and Frogger.

FPGAs have a bit of a higher learning curve than something as simple as the Arduino, but ultimately much more powerful and flexible. Very cool, and at an attractive price point.

Papilio.

Welcome 2011, with some project ideas…

Hope everyone has had a wonderful holiday. I must admit that my own vacation wasn’t productive in the sense of completing projects: I spent far too much time sleeping in, relaxing and playing far too much Epic Mickey on my Wii. But I have also spent some time thinking about the past year and year to come with respect to the kind of fun projects that I like to do.

2010 wasn’t actually a banner year for my outside projects. I did a few smallish programming projects (mostly having to do with generating simple sounds). Tom and I managed to loft a camera on a kite once. I simulated some rainbows. I gathered some parts for a high altitude balloon launch. I bought an FPGA board and got it to blink some LEDs, but made relatively little traction on my ultimate goal of implementing a processor. And I did relatively little amateur radio.

So, here’s my list of projects that I’d like to see completed in 2011.

A high altitude balloon launch. It seems now that everyone is doing these, but I still would like to do one. I’ve got an OpenTracker to provide the APRS downlink, and have radios and cameras that could be used. What’s really required is for me to dedicate time to the construction and testing of the completed payload, and then start working on getting the necessary helium tank rentals and balloons. This would be a great project to fly in the summer when the cloud cover is minimal. Maybe a 4th of July launch?

Homebrew a radio. I did manage to get closer to finishing some of my kits over the vacation, but I’m increasingly dissatisfied with assembling PC boards as an intellectual activity. For one thing, if you make a mistake, desoldering and replacing components on a PCB is annoying, particularly when the PC board has been optimized for area by packing as many components onto a board as possible. But more than that, the PCB approach means that your design is fixed: modifications aren’t there to be explored. Classic fabrication techniques such as “Ugly” or “Manhattan” construction means that you can simply add or change components, and still arrive at RF circuits which perform well.

So, here’s my idea: construct a radio (receiver more important than transmitter) as a series of modules constructed with Manhattan style construction on a number of small boards. Concentrate on learning how each part functions and can be tested. Try to use common, inexpensive components. Make the final radio lunchbox size, rather than Altoid size, because that means we’ll have extra space to make modifications. Concentrate on improving your test equipment and the testing techniques.

Antennas. I live in one of those places with restrictive CC&Rs. In addition, the terrain of my lot presents some significant challenges. Currently, most of my ham radio operation is antenna limited: without better ability to hear signals, there is little point in beaming out more power. I’ve been reading a lot about small antennas (transmitting loops, helically wound verticals and short verticals). Develop and test some of these, perhaps using WSPR beacon operations using different antennas as comparisons.

FPGA cpus. I’ve wanted to learn about FPGA techniques to design a CPU for years. I now have a BASYS2 board from digilentinc, and while I’ve gotten it to blink some LEDs, I’m quite a long way from making a CPU. I have a feeling this project will linger on for quite some time, but I’m keeping it on the list.

Experiment with the Kinect. Carmen got me a Kinect for Christmas. I have a couple of projects that I want to keep under my hat until I make some progress on them, but it is a gadget with lots of hacking potential.

Meta issues. It dawns on me that part of my problem isn’t coming up with project ideas, it’s figuring out how to accomplish them. First of all, there are the usual problems of productivity. Balancing work and home life with the requirements of your hobby activities. I’m not always good at that. But I also think also that I spend a great deal of time working in isolation, and seeking out other enthusiasts, collaborators and mentors would significantly enhance my productivity. I’ll be working on that in 2011 as well.

If you made it this far, what are your projects that you’d like to see done in 2011? Either scribble them in comments, or make a post on your own blog or whatever and link them in the comments.

The J1 Forth CPU, running on an FPGA

Tom showed me a link to The J1 Forth CPU, a very small processor which is coded in Verilog (only 200 lines!) and can run very fast on existing FPGA boards.

It is quite an intriguing design.

Forth is an intriguing if somewhat archaic programming language. In the bygone ages of my youth, I experimented a bit with FigForth on my Atari 400, which I found to be a pretty interesting and fun programming environment, but I found most Forth code to be rather inscrutable and hard to understand, at least, it was hard if you let more than a few days pass between when you wrote it and when you read it. Nevertheless, I don’t particularly fear Forth, and have used another somewhat similar language, namely Postscript, off and on over the years.

Forth is a stack-oriented language. In languages such as C, we are used to having a call-stack which contains not just return addresses, but also local variables. Forth is a different in that local variables aren’t typically stored on the stack. Instead, Forth splits things that C would place on a single stack into two separate stacks: the data stack (often just called “the stack”) and the return stack (or “rstack”). Forth “words” (procedures) generally specify actions that manipulate one or both stacks. For instance, the “plus” word, might take the two values at the top of the data stack and replace them with their sum. The “exit” or “;” word pulls a return address off the rstack, and transfers it to the IP (instruction pointer, basically the PC).

The J1 architecture is reasonably novel in that is optimized for the execution of Forth. It is a 16 bit machine, which has an internal state consisting of a 33 (not sure why not 32, but that’s what the docs say) deep data stack, a 32 deep return stack, and a 13 bit program counter. No condition flags, modes, or registers. It has 8K words (16 bit words) of RAM, and an additional 8K words for memory mapped I/O. Instructions fall into one of 5 classes:

If the MSB of the instruction is a one, the remaining 15 bits specify a literal value which is pushed onto the data stack.< ./li>
If the upper three bits are all zero, then the remaining 13 bits specify a new value for the PC (an unconditional jump).
If the upper three bits are “001”, then the machine pops the data stack, and if the value is zero, the remaining 13 bits specify the new PC (conditional jump).
If the upper three bits are “010”, then the remaining 13 bits specify a call address. The current PC is pushed to the return stack, and the remaining 13 bits specify the new PC.
The remaining case (upper three bits “011”) specify an ALU instruction. This single instruction can implement many Forth words directly. The remaining 13 bits are split into 7 fields which together specify a complex action. Four bits pick one of 16 operations that are performed on the top value (and for binary operations, the next value) of the stack. A single bits says whether the top value should be copied to the next value on the data stack. Another bit specifies whether the return address should be copied to the PC. Another bit specifies whether the top of the data stack should get copied to the rstack. Two two-bit fields give a set of signed increments/decrements for the data and rstack. And a last bit specifies if a RAM store operation should happen (the next value gets stored in the address pointed at by the top value).

And that’s pretty much it! Many basewords are very, very simple and can be implemented in just one or two op codes. The resulting machine runs very fast. It’s really quite clever: all the more so because it’s actually possible to understand how it works.

It actually is fairly close to the Hack Platform defined in Noam Nisan and Shimon Schocken’s book “The Elements of Computing Systems”. The “Hack” machine has only two kinds of instructions: an “address” instruction (similar to the literal instruction above) and the “compute” instruction, similar to the last: it specifies what function the ALU computes, the destination for the ALU, and a jump condition. They use this chip to implement a more conventional stack-based virtual machine. The two machines have similar specifications and power.

I found them both to be interesting. I’ll be reading the J1 Verilog code closely.

LatticeXP2 Brevia Development Kit, with a deal breaker

I’ve been playing with a BASYS2 FPGA development kit from digilentinc.com, and pondering the world of digital system design. I chose the BASYS2 because of its low price ($70) and because it included a reasonable number of LEDs, switches, a VGA interface and a connector for a PS/2 keyboard. Still, I’ve been looking for other small, reasonably priced FPGA kits, perhaps even ones which aren’t based on the Xilinx chips. Today I learned of a nice looking little $49 kit from Lattice:

LatticeXP2 Brevia Development Kit.

While it doesn’t include the VGA or PS/2 interfaces, it does include a 1Mbit static ram on board, which perhaps makes it more interesting for experimenting with FPGA cpus. But here’s the thing: it includes a parallel port programming cable, and literally no computers I currently use have a parallel port anymore. They tel you that you need a special USB cable: the HW-USBN-2A which is not included. Oh well, think I, that can’t be too bad…

That cable costs $149.

Yes, the programming cable for this FPGA board is 3x the cost of the entire board.

Deal, broken.